NDLI: Gain scheduled neural network tuned pi feedback control system for the lansce accelerator

Content Provider	IEEE Xplore Digital Library
Author	Sungil Kwon Davis, J. Lynch, M. Prokop, M. Ruggles, S. Torrez, P.
Copyright Year	2007
Description	Author affiliation: LANL, Los Alamos (Sungil Kwon; Davis, J.; Lynch, M.; Prokop, M.; Ruggles, S.; Torrez, P.)
Abstract	The current LANSCE LLRF system is an analog PI Feedback control system which achieves the amplitude and phase error within 1% and 1 degree. The feedback system receives the cavity amplitude and phase and the crosstalk between the amplitude and the phase paths is significant. We propose an In-phase (I) and Quadrature (Q) based feedback control system which easily decouples the crosstalk of I and Q channels. A gain scheduled PI feedback controller with optimally generated set point trajectory reduces the transient peak of the feedback controller and hence reduce the fatigue of the RF amplifier chain. An additional feature of the controller is the Neural network based self-tuning PI feedback, where the neural network tunes the feedback gains to minimize the errors in the least squares sense. The proposed control system is implemented with Altera Stratix II FPGA. The control system is modeled with DSP Builder and automatically generates HDL. Altera SOPC Builder is used for the hardware integration of the DSP Builder model, memories, peripherals, and 32 bit NIOS II embedded processor. NIOS II processor equipped with real time operating system communicates with the host computer via Ethernet, uploads data, computes parameters, and downloads parameters. The proposed control system is tested with the low power test-stand for the robustness of the algorithm.
Starting Page	2379
Ending Page	2381
File Size	401494
Page Count	3
File Format	PDF
ISBN	9781424409167
DOI	10.1109/PAC.2007.4441256
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Neural networks Feedback control Acceleration Neurofeedback Error correction Crosstalk Adaptive control Automatic control Control systems Digital signal processing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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