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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Lorenzo, J.A. Pichel, J.C. LaFrance-Linden, D. Rivera, F.F. Singh, D.E. |
| Copyright Year | 2010 |
| Abstract | This work presents a study undertaken to characterise the behaviour of some parallelisation techniques for irregular codes, previously developed for SMP architectures, on a several-node SMP NUMA system. The main objective is to determine the performance effect of bus contention and cache coherency in such a complex architecture. Results show that: (1) cores which share a socket can be considered as independent processors in this context; (2) for big data sizes, the effect of sharing a bus degrades the performance but masks the cache coherency effects and (3) the NUMA-ratio is a critical factor on irregular codes. These results allow us to study the effect in performance of the thread-to-core mappings and memory allocation policies. |
| Starting Page | 213 |
| Ending Page | 217 |
| File Size | 228904 |
| Page Count | 5 |
| File Format | |
| ISBN | 9781424456727 |
| ISSN | 10666192 |
| e-ISBN | 9781424456734 |
| DOI | 10.1109/PDP.2010.66 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2010-02-17 |
| Publisher Place | Italy |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Sparse matrices Multicore processing Computer architecture Testing Computer science Informatics Computer networks Concurrent computing Distributed computing Sockets Hardware Counters Irregular Codes Itanium2 |
| Content Type | Text |
| Resource Type | Article |
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