NDLI: Routing tree construction for interconnection networks with irregular topologies

Content Provider	IEEE Xplore Digital Library
Author	Hsin-Chou Chi Wen-Jen Wu
Copyright Year	2003
Description	Author affiliation: Dept. of Comput. Sci. & Inf. Eng., Nat. Dong Hwa Univ., Hualien, Taiwan (Hsin-Chou Chi; Wen-Jen Wu)
Abstract	High-throughput low-latency interconnection networks are suitable for workstation clusters. An interconnection network can be constructed in different topologies. Typically, interconnection networks with regular topologies, such as mesh, torus, and hypercube, are less scalable for workstation clusters than those with irregular topologies. There have been many deadlock-free routing algorithms developed for regular networks, but it is relatively difficult to solve deadlock problems for irregular networks. We have previously proposed an effective routing scheme, called TRAIN, for irregular networks. The TRAIN routing algorithm is deadlock-free and requires no routing tables in the switch. This routing algorithm is based on a spanning tree which is constructed in the network. In this paper, we study how to construct a spanning tree so that the network can benefit from the TRAIN routing algorithm. Several schemes of constructing spanning trees are studied. These tree construction schemes are evaluated and compared in unloaded networks based on static analysis. They are also evaluated for loaded networks based on simulations.
Sponsorship	IMATI - CNR Genova Eur. Commission Inf. Soc. Technol. Programme (Grant no. IST-2001-92548)
Starting Page	157
Ending Page	164
File Size	307664
Page Count	8
File Format	PDF
ISBN	0769518753
ISSN	10666192
DOI	10.1109/EMPDP.2003.1183582
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-02-05
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Routing Multiprocessor interconnection networks Network topology Switches Communication switching System recovery Workstations Clustering algorithms Delay Hypercubes
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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