NDLI: In-Place Data Sliding Algorithms for Many-Core Architectures

Content Provider	IEEE Xplore Digital Library
Author	Gomez Luna, J. Li-Wen Chang I-Jui Sung Wen-Mei Hwu Guil, N.
Copyright Year	2015
Description	Author affiliation: Electr. & Comput. Eng., Univ. of Illinois at Urbana-Champaign, Urbana, IL, USA (Li-Wen Chang; Wen-Mei Hwu) \|\| Comput. Archit., Univ. of Malaga, Malaga, Spain (Guil, N.) \|\| Comput. Archit. & Electron., Univ. of Cordoba, Cordoba, Spain (Gomez Luna, J.) \|\| MulticoreWare, Inc., Champaign, IL, USA (I-Jui Sung)
Abstract	In-place data manipulation is very desirable in many-core architectures with limited on-board memory. This paper deals with the in-place implementation of a class of primitives that perform data movements in one direction. We call these primitives Data Sliding (DS) algorithms. Notable among them are relational algebra primitives (such as select and unique), padding to insert empty elements in a data structure, and stream compaction to reduce memory requirements. Their in-place implementation in a bulk synchronous parallel model, such as GPUs, is specially challenging due to the difficulties in synchronizing threads executing on different compute units. Using a novel adjacent work-group synchronization technique, we propose two algorithmic schemes for regular and irregular DS algorithms. With a set of 5 benchmarks, we validate our approaches and compare them to the state-of-the-art implementations of these benchmarks. Our regular DS algorithms demonstrate up to 9.11x and 73.25x on NVIDIA and AMD GPUs, respectively, the throughput of their competitors. Our irregular DS algorithms outperform NVIDIA Thrust library by up to 3.24x on the three most recent generations of NVIDIA GPUs.
Starting Page	210
Ending Page	219
File Size	4970825
Page Count	10
File Format	PDF
ISBN	9781467375870
ISSN	01903918
DOI	10.1109/ICPP.2015.30
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-09-01
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Synchronization Arrays Graphics processing units Parallel processing Compaction Memory management relational algebra in-place stream compaction
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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