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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Matsutani, H. Koibuchi, M. Amano, H. |
| Copyright Year | 2007 |
| Description | Author affiliation: Keio Univ., Yokohama (Matsutani, H.) |
| Abstract | Three-dimensional network-on-chip (3-D NoC) is an emerging research topic exploring the network architecture of 3-D ICs that stack several smaller wafers for reducing wire length and wire delay. Although the network topology of 3-D NoC has been explored for a couple of years, there is still only a narrow range of choices. In this paper, we propose a class of 3-D topologies called Xbar-connected network-on-tiers (XNoTs), which consist of multiple network layers tightly connected via crossbar switches. To make the best use of the short delay and high density of inter-wafer links, XNoTs topologies have crossbar switches that connect different layers and their cores. The planar topology on every layer can be independently customized so as to meet the cost-performance requirements, as far as network connectivity is at least guaranteed with the bottom layer. We also propose their routing algorithm, which guarantees deadlock-freedom by restricting the inter-layer packet transfer from a lower-numbered layer to a higher-numbered layer. Path sets at the bottom layer close to the heat sink of the chip can be selectively employed in order to mitigate the heat-dissipation problem of 3-D ICs. Several forms of XNoTs topologies including meshes, tori, and/or trees are created, and they are evaluated in terms of performance, cost, and energy consumption. As a result, we show that even with the flexibilities mentioned above, XNoTs achieve at least as high throughput as existing 3-D topologies for equivalent chip sizes. |
| Sponsorship | Int. Assoc. Comput. Commun. |
| Starting Page | 75 |
| Ending Page | 75 |
| File Size | 296925 |
| Page Count | 1 |
| File Format | |
| ISSN | 01903918 |
| DOI | 10.1109/ICPP.2007.79 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-09-10 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Network-on-a-chip Network topology Wire Switches Heat sinks Delay Routing System recovery Costs Energy consumption |
| Content Type | Text |
| Resource Type | Article |
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