NDLI: Memory Reference Behavior of Compiler Optimized Programs on High Speed Architectures

Content Provider	IEEE Xplore Digital Library
Author	Fu, John W. C. Patel, Janak H.
Copyright Year	1993
Description	Author affiliation: Intel Corporation, Folsom, CA (Fu, John W. C.) \|\| University of Illinois at Urbana-Champaign (Patel, Janak H.)
Abstract	High speed architectures usually employ some form of parallelism or concurrency. Parallel or concurrent execution of a program not only increases the rate at which references are issued to the memory system but also changes the behavior of these references, relative to its serial-scalar execution. This paper reports the variations in program memory reference behavior when automatically transformed by a compiler and executed on parallel and vector archirectures. Using traces of the PERFECT benchmark set, executed on on Aliiant FX180 in a single scalar processor, single vector processor, scalar multiprocessor and vector multiprocessor modes, measurements are reported for issue rates, reference locality and data sharing.
Starting Page	87
Ending Page	94
File Size	1507953
Page Count	8
File Format	PDF
ISBN	0849389836
DOI	10.1109/ICPP.1993.114
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-08-16
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Program processors Optimizing compilers Parallel processing Registers Concurrent computing Vector processors Cities and towns Virtual reality Cache memory Bandwidth
Content Type	Text
Resource Type	Article

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