NDLI: Performance Analysis and Optimization of Parallel Scientific Applications on CMP Cluster Systems

Content Provider	IEEE Xplore Digital Library
Author	Xingfu Wu Taylor, V. Lively, C. Sharkawi, S.
Copyright Year	2008
Description	Author affiliation: Dept. of Comput. Sci., Texas A&M Univ., College Station, TX (Xingfu Wu; Taylor, V.; Lively, C.; Sharkawi, S.)
Abstract	Chip multiprocessors (CMP) are widely used for high performance computing. Further, these CMPs are being configured in a hierarchical manner to compose a node in a cluster system. A major challenge to be addressed is efficient use of such cluster systems for large-scale scientific applications. In this paper, we quantify the performance gap resulting from using different number of processors per node; this information is used to provide a baseline for the amount of optimization needed when using all processors per node on CMP clusters. We conduct detailed performance analysis to identify how applications can be modified to efficiently utilize all processors per node on CMP clusters, especially focusing on two scientific applications: a 3D particle-in-cell, magnetic fusion application gyrokinetic toroidal code (GTC) and a lattice Boltzmann method for simulating fluid dynamics (LBM). In terms of refinements, we use conventional techniques such as cache blocking, loop unrolling and loop fusion, and develop hybrid methods for optimizing MPI_Allreduce and MPI_Reduce. Using these optimizations, the application performance for utilizing all processors per node was improved by up to 18.97% for GTC and 15.77% for LBM on up to 2048 total processors on the CMP clusters.
Starting Page	188
Ending Page	195
File Size	490760
Page Count	8
File Format	PDF
ISBN	9780769533759
ISSN	15302016
DOI	10.1109/ICPP-W.2008.21
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Program processors Optimization Bandwidth Supercomputers Three dimensional displays Bidirectional control Clustering algorithms cluster system Performance Analysis Performance Optimization parallel scientific applications chip multiprocessors
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Three-dimensional multiprocessor system-on-chip thermal optimization

Hybrid Parallel Bidirectional Sieve Based on SMP Cluster

A Computation- and Communication-Optimal Parallel Direct 3-Body Algorithm

Performance analysis and optimization of parallel scientific applications on CMP cluster systems (2008)

Hierarchical Parallel Matrix Multiplication on Large-Scale Distributed Memory Platforms

Extending OpenMP for heterogeneous chip multiprocessors

Hardware-software co-design of 3D data compression for real-time ultrasonic imaging applications

Change Function of 2D/3D Network-on-Chip

Simulating SiScape: A Parallel CMP Architecture

Performance Analysis and Optimization of Parallel Scientific Applications on CMP Cluster Systems

Similar Documents

Three-dimensional multiprocessor system-on-chip thermal optimization

Hybrid Parallel Bidirectional Sieve Based on SMP Cluster

A Computation- and Communication-Optimal Parallel Direct 3-Body Algorithm

Performance analysis and optimization of parallel scientific applications on CMP cluster systems (2008)

Hierarchical Parallel Matrix Multiplication on Large-Scale Distributed Memory Platforms

Extending OpenMP for heterogeneous chip multiprocessors

Hardware-software co-design of 3D data compression for real-time ultrasonic imaging applications

Change Function of 2D/3D Network-on-Chip

Simulating SiScape: A Parallel CMP Architecture

Performance Analysis and Optimization of Parallel Scientific Applications on CMP Cluster Systems