NDLI: Powerful and feasible processor interconnections with an evaluation of their communications capabilities

Content Provider	IEEE Xplore Digital Library
Author	Qiang Wang Ziavras, S.G.
Copyright Year	1999
Description	Author affiliation: Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA (Qiang Wang)
Abstract	Scalable networks with very good topological properties are often impossible to build because of their prohibitively high wiring complexity. Such a network is the generalized hypercube (GH). It supports full-connectivity of all its nodes in each dimension and is characterized by outstanding topological properties. We propose a new class of scalable interprocessor connections, namely HOWs (Highly-Overlapping Windows), capable of lower complexity than GHs and comparable performance. HOWs are obtained from GHs by removing edges to produce systems of lower wiring complexity. They contain numerous highly-overlapping GHs of smaller size. The classical GH belongs to this new class of interconnections. We demonstrate that 2-DHOWs perform much better than binary hypercubes for important communications patterns.
Starting Page	222
Ending Page	227
File Size	240891
Page Count	6
File Format	PDF
ISBN	0769502318
ISSN	10874089
DOI	10.1109/ISPAN.1999.778943
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-06-23
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hypercubes Wiring Scalability Wires Switches Computational Intelligence Society Very large scale integration Cost function Emulation Broadcast technology
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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