NDLI: DeNovo: Rethinking the Memory Hierarchy for Disciplined Parallelism

Content Provider	IEEE Xplore Digital Library
Author	Byn Choi Komuravelli, R. Hyojin Sung Smolinski, R. Honarmand, N. Adve, S.V. Adve, V.S. Carter, N.P. Ching-Tsun Chou
Copyright Year	2011
Abstract	For parallelism to become tractable for mass programmers, shared-memory languages and environments must evolve to enforce disciplined practices that ban "wild shared-memory behaviors;'' e.g., unstructured parallelism, arbitrary data races, and ubiquitous non-determinism. This software evolution is a rare opportunity for hardware designers to rethink hardware from the ground up to exploit opportunities exposed by such disciplined software models. Such a co-designed effort is more likely to achieve many-core scalability than a software-oblivious hardware evolution. This paper presents DeNovo, a hardware architecture motivated by these observations. We show how a disciplined parallel programming model greatly simplifies cache coherence and consistency, while enabling a more efficient communication and cache architecture. The DeNovo coherence protocol is simple because it eliminates transient states -- verification using model checking shows 15X fewer reachable states than a state-of-the-art implementation of the conventional MESI protocol. The DeNovo protocol is also more extensible. Adding two sophisticated optimizations, flexible communication granularity and direct cache-to-cache transfers, did not introduce additional protocol states (unlike MESI). Finally, DeNovo shows better cache hit rates and network traffic, translating to better performance and energy. Overall, a disciplined shared-memory programming model allows DeNovo to seamlessly integrate message passing-like interactions within a global address space for improved design complexity, performance, and efficiency.
Starting Page	155
Ending Page	166
File Size	446309
Page Count	12
File Format	PDF
ISBN	9781457717949
ISSN	1089795X
DOI	10.1109/PACT.2011.21
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-10
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Protocols Hardware Coherence Software Transient analysis Arrays Programming
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Hardware and Architecture Software

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