NDLI: A generalized basic cycle calculation method for efficient array redistribution

Content Provider	IEEE Xplore Digital Library
Author	Yeh-Ching Chung Sheng-Wen Bai Ching-Hsien Hsu Chu-Sing Yang
Copyright Year	1998
Description	Author affiliation: Dept. of Inf. Eng., Feng Chia Univ., Taichung, Taiwan (Yeh-Ching Chung)
Abstract	In many scientific applications, dynamic array redistribution is usually required to enhance the performance of an algorithm. We present a generalized basic cycle calculation (GBCC) method to efficiently perform a BLOCK-CYCLIC(s) over P processors to BLOCK-CYCLIC(t) over Q processors array redistribution. In the GBCC method, a processor first computes the source/destination processor/data sets of array elements in the first generalized basic cycle of the local array it owns. A generalized basic cycle is defined as lcm(sP,tQ)/(gcd(s,t)/spl times/P) in the source distribution and lcm(sP,tQ)/(gcd(s,t)/spl times/Q) in the destination distribution. From the source/destination processor/data sets of array elements in the first generalized basic cycle, we can construct packing/unpacking pattern tables. Based on the packing/unpacking pattern tables, a processor can pack/unpack array elements efficiently. To evaluate the performance of the GBCC method, we have implemented this method on an IBM SP2 parallel machine, along with the PITFALLS method and the ScaLAPACK method. The cost models for these three methods are also presented. The experimental results show that the GBCC method outperforms the PITFALLS method and the ScaLAPACK method for all test samples. A brief description of the extension of the GBCC method to multi dimensional array redistributions is also presented.
Starting Page	640
Ending Page	647
File Size	1106929
Page Count	8
File Format	PDF
ISBN	0818686030
ISSN	15219097
DOI	10.1109/ICPADS.1998.741147
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-12-14
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parallel machines Costs Testing
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture

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