NDLI: DVS: an object-oriented framework for distributed Verilog simulation

Content Provider	IEEE Xplore Digital Library
Author	Li, L. Huang, H. Tropper, C.
Copyright Year	2003
Description	Author affiliation: Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada (Li, L.; Huang, H.; Tropper, C.)
Abstract	There is a wide spread usage of hardware design languages (HDL) to speed up the time to market for the design of modern digital systems. Verification engineers can simulate hardware in order to verify its performance and correctness with help of an HDL. However, simulation can't keep pace with the growth in size and complexity of circuits and has become a bottleneck of the design process. Distributed HDL simulation on a cluster of workstations has the potential to provide a cost effective solution to this problem. We describe the design and implementation of DVS, an object-oriented framework for distributed Verilog simulation. Verilog is an HDL which sees wide industrial use. DVS is an outgrowth of clustered time warp, originally developed for logic simulation. The design of the framework emphasizes simplicity and extensibility and aims to accommodate experiments involving partitioning and dynamic load balancing. Preliminary results obtained by simulating a 16 bit multiplier are presented.
Sponsorship	IEEE Comput. Soc. Tech. Commitee on Simulation ACM Special Interest Group on Simulation Soc. for Modelling and Simulation Int
Starting Page	173
Ending Page	180
File Size	301944
Page Count	8
File Format	PDF
ISBN	0769519709
ISSN	10874097
DOI	10.1109/PADS.2003.1207433
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-06-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Voltage control Hardware design languages Object oriented modeling Circuit simulation Time to market Digital systems Systems engineering and theory Process design Workstations Costs
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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