NDLI: A multidimensional study on the feasibility of parallel switch-level circuit simulation

Content Provider	IEEE Xplore Digital Library
Author	Yu-An Chen Jha, V. Bagrodia, R.
Copyright Year	1997
Description	Author affiliation: Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA (Yu-An Chen)
Abstract	This paper presents the results of an experimental study to evaluate the effectiveness of multiple synchronization protocols and partitioning algorithms in reducing the execution time of switch-level models of VLSI circuits. Specific contributions of this paper include: parallelizing an existing switch-level simulator such that the model can be executed using conservative and optimistic simulation protocols with minor changes; evaluating effectiveness of several partitioning algorithms for parallel simulation; and demonstrating speedups with both conservative and optimistic simulation protocols for seven circuits, ranging in size from 3 K transistors to about 87 K transistors.
Starting Page	46
Ending Page	54
File Size	1019394
Page Count	9
File Format	PDF
ISBN	0818679646
DOI	10.1109/PADS.1997.594585
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-06-10
Publisher Place	Austria
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multidimensional systems Switching circuits Circuit simulation Protocols Concurrent computing Very large scale integration Switches Timing Context modeling Manuals
Content Type	Text
Resource Type	Article

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