NDLI: Exploring Data Staging Across Deep Memory Hierarchies for Coupled Data Intensive Simulation Workflows

Content Provider	IEEE Xplore Digital Library
Author	Tong Jin Fan Zhang Qian Sun Hoang Bui Romanus, M. Podhorszki, N. Klasky, S. Kolla, H. Chen, J. Hager, R. Choong-Seock Chang Parashar, M.
Copyright Year	2015
Description	Author affiliation: Oak Ridge Nat. Labortory, Oak Ridge, TN, USA (Podhorszki, N.; Klasky, S.) \|\| Princeton Plasma Phys. Lab., Princeton, NJ, USA (Hager, R.; Choong-Seock Chang) \|\| NSF Cloud & Autonomic Comput. Center, Rutgers Univ., Piscataway, NJ, USA (Tong Jin; Fan Zhang; Qian Sun; Hoang Bui; Romanus, M.; Parashar, M.) \|\| Sandia Nat. Labortory, Livermore, CA, USA (Kolla, H.; Chen, J.)
Abstract	As applications target extreme scales, data staging and in-situ/in-transit data processing have been proposed to address the data challenges and improve scientific discovery. However, further research is necessary in order to understand how growing data sizes from data intensive simulations coupled with the limited DRAM capacity in High End Computing systems will impact the effectiveness of this approach. In this paper, we explore how we can use deep memory levels for data staging, and develop a multi-tiered data staging method that spans bothDRAM and solid state disks (SSD). This approach allows us to support both code coupling and data management for data intensive simulation workflows. We also show how an adaptive application-aware data placement mechanism can dynamically manage and optimize data placement across the DRAM ands storage levels in this multi-tiered data staging method. We present an experimental evaluation of our approach using wolf resources: an Infiniband cluster (Sith) and a Cray XK7system (Titan), and using combustion (S3D) and fusion (XGC1) simulations.
Starting Page	1033
Ending Page	1042
File Size	794007
Page Count	10
File Format	PDF
ISBN	9781479986491
ISSN	15302075
DOI	10.1109/IPDPS.2015.50
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-05-25
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Data models Random access memory Computational modeling Analytical models Numerical models Runtime Couplings coupling Data management adaptation data placement ssd deep memory hierarchy data staging multi-tiered exascale
Content Type	Text
Resource Type	Article

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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