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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Gharaibeh, A. Beltrão Costa, L. Santos-Neto, E. Ripeanu, M. |
| Copyright Year | 2013 |
| Description | Author affiliation: Dept. of Electr. & Comput. Eng., Univ. of British Columbia, Vancouver, BC, Canada (Gharaibeh, A.; Beltrão Costa, L.; Santos-Neto, E.; Ripeanu, M.) |
| Abstract | Graph processing has gained renewed attention. The increasing large scale and wealth of connected data, such as those accrued by social network applications, demand the design of new techniques and platforms to efficiently derive actionable information from large scale graphs. Hybrid systems that host processing units optimized for both fast sequential processing and bulk processing (e.g., GPUaccelerated systems) have the potential to cope with the heterogeneous structure of real graphs and enable high performance graph processing. Reaching this point, however, poses multiple challenges. The heterogeneity of the processing elements (e.g., GPUs implement a different parallel processing model than CPUs and have much less memory) and the inherent irregularity of graph workloads require careful graph partitioning and load assignment. In particular, the workload generated by a partitioning scheme should match the strength of the processing element the partition is allocated to. This work explores the feasibility and quantifies the performance gains of such low-cost partitioning schemes. We propose to partition the workload between the two types of processing elements based on vertex connectivity. We show that such partitioning schemes offer a simple, yet efficient way to boost the overall performance of the hybrid system. Our evaluation illustrates that processing a 4-billion edges graph on a system with one CPU socket and one GPU, while offloading as little as 25% of the edges to the GPU, achieves 2x performance improvement over state-of-the-art implementations running on a dual-socket symmetric system. Moreover, for the same graph, a hybrid system with dualsocket and dual-GPU is capable of 1.13 Billion breadth-first search traversed edge per second, a performance rate that is competitive with the latest entries in the Graph500 list, yet at a much lower price point. |
| Sponsorship | IEEE Comput. Soc. |
| Starting Page | 851 |
| Ending Page | 862 |
| File Size | 1057235 |
| Page Count | 12 |
| File Format | |
| ISBN | 9781467360661 |
| ISSN | 15302075 |
| DOI | 10.1109/IPDPS.2013.37 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-05-20 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Graphics processing units Partitioning algorithms Computational modeling Parallel processing Hardware Kernel Algorithm design and analysis Workload Partitioning GPUs Graphs Breadth-first Search PageRank Hybrid System |
| Content Type | Text |
| Resource Type | Article |
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