NDLI: Fisheye lens distortion correction on multicore and hardware accelerator platforms

Content Provider	IEEE Xplore Digital Library
Author	Daloukas, K. Antonopoulos, C.D. Bellas, N. Chai, S.M.
Copyright Year	2010
Description	Author affiliation: Motorola, Inc., Schaumburg, IL, USA (Chai, S.M.) \|\| Department of Computer and Communications Engineering, University of Thessaly, Volos, Greece (Daloukas, K.; Antonopoulos, C.D.; Bellas, N.)
Abstract	Wide-angle (fisheye) lenses are often used in virtual reality and computer vision applications to widen the field of view of conventional cameras. Those lenses, however, distort images. For most real-world applications the video stream needs to be transformed, at real-time (20 frames/sec or better), back to the natural-looking, central perspective space. This paper presents the implementation, optimization and characterization of a fisheye lens distortion correction application on three platforms: a conventional, homogeneous multicore processor by Intel, a heterogeneous multicore (Cell BE), and an FPGA implementing an automatically generated streaming accelerator. We evaluate the interaction of the application with those architectures using both high- and low-level performance metrics. In macroscopic terms, we find that todays mainstream conventional multicores are not effective in supporting real-time distortion correction, at least not with the currently commercially available core counts. Architectures, such as the Cell BE and FPGAs, offer the necessary computational power and scalability, at the expense of significantly higher development effort. Among these three platforms, only the FPGA and a fully optimized version of the code running on the Cell processor can provide realtime processing speed. In general, FPGAs meet the expectations of performance, flexibility, and low overhead. General purpose multicores are, on the other hand, much easier to program.
Starting Page	1
Ending Page	10
File Size	1238757
Page Count	10
File Format	PDF
ISBN	9781424464425
ISSN	15302075
e-ISBN	9781424464432
DOI	10.1109/IPDPS.2010.5470360
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Lenses Multicore processing Hardware Field programmable gate arrays Application software Computer architecture Virtual reality Computer vision Cameras Streaming media Performance Evaluation Cell FPGA Image Warping
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A fisheye distortion correction algorithm optimized for hardware implementations

Real-Time Fisheye Lens Distortion Correction Using Automatically Generated Streaming Accelerators

FPGA based real time video distortion correction

Dynamic-SIMD for lens distortion compensation

Fisheye Video Correction

High-Speed Simultaneous Image Distortion Correction Transformations for a Multicamera Cylindrical Panorama Real-time Video System Using FPGA

Real-Time Image Distortion Correction using FPGA-based System

Spatial Optical Distortion Correction in an FPGA

FPGA architecture for real-time barrel distortion correction of colour images

Fisheye lens distortion correction on multicore and hardware accelerator platforms

Similar Documents

A fisheye distortion correction algorithm optimized for hardware implementations

Real-Time Fisheye Lens Distortion Correction Using Automatically Generated Streaming Accelerators

FPGA based real time video distortion correction

Dynamic-SIMD for lens distortion compensation

Fisheye Video Correction

High-Speed Simultaneous Image Distortion Correction Transformations for a Multicamera Cylindrical Panorama Real-time Video System Using FPGA

Real-Time Image Distortion Correction using FPGA-based System

Spatial Optical Distortion Correction in an FPGA

FPGA architecture for real-time barrel distortion correction of colour images

Fisheye lens distortion correction on multicore and hardware accelerator platforms