NDLI: NQueens on CUDA: Optimization Issues

Content Provider	IEEE Xplore Digital Library
Author	Feinbube, F. Rabe, B. von Löwis, M. Polze, A.
Copyright Year	2010
Abstract	Todays commercial off-the-shelf computer systems are multicore computing systems as a combination of CPU, graphic processor (GPU) and custom devices. In comparison with CPU cores, graphic cards are capable to execute hundreds up to thousands compute units in parallel. To benefit from these GPU computing resources, applications have to be parallelized and adapted to the target architecture. In this paper we show our experience in applying the NQueens puzzle solution on GPUs using Nvidia's CUDA (Compute Unified Device Architecture) technology. Using the example of memory usage and memory access, we demonstrate that optimizations of CUDA programs may have contrary results on different CUDA architectures. Evaluation results will point out, that it is not sufficient to use new programming languages or compilers to achieve best results with emerging graphic card computing.
Starting Page	63
Ending Page	70
File Size	439119
Page Count	8
File Format	PDF
ISBN	9781424476022
e-ISBN	9781424476015
DOI	10.1109/ISPDC.2010.22
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-07-07
Publisher Place	Turkey
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Concurrent computing Computer architecture Distributed computing Multicore processing Computer graphics Computer languages Field programmable gate arrays Computer applications Application software Program processors memory access trade-off GPGPU
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Reconfigurable processing with field programmable gate arrays

Fast locally consistent dense stereo on multicore

RAMP: Research Accelerator for Multiple Processors

Sparse Graph Processing with Soft-Processors

Modeling memory resources distribution on multicore processors using games on cellular automata lattices

A Behavioral Synthesis Approach for Distributed Memory FPGA Architectures

Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors

A Multicore Architecture for High-Performance Scientific Computing Using FPGAs

Accelerating Algebraic Reconstruction Using CUDA-Enabled GPU

NQueens on CUDA: Optimization Issues

Similar Documents

Reconfigurable processing with field programmable gate arrays

Fast locally consistent dense stereo on multicore

RAMP: Research Accelerator for Multiple Processors

Sparse Graph Processing with Soft-Processors

Modeling memory resources distribution on multicore processors using games on cellular automata lattices

A Behavioral Synthesis Approach for Distributed Memory FPGA Architectures

Performance comparison of single-precision SPICE Model-Evaluation on FPGA, GPU, Cell, and multi-core processors

A Multicore Architecture for High-Performance Scientific Computing Using FPGAs

Accelerating Algebraic Reconstruction Using CUDA-Enabled GPU

NQueens on CUDA: Optimization Issues