NDLI: Understanding the Memory Behavior of Emerging Multi-core Workloads

Content Provider	IEEE Xplore Digital Library
Author	Junmin Lin Yu Chen Wenlong Li Jaleel, A. Zhizhong Tang
Copyright Year	2009
Abstract	This paper characterizes the memory behavior on emerging RMS (recognition, mining, and synthesis) workloads for future multi-core processors. As multi-core processors proliferate across different application domains, and the number of on-die cores continues to increase, a key issue facing processor architects is the design of the on-die last level cache (LLC). In this paper, we explore the LLC design space for multi-threaded RMS workloads by examining the working set sizes, data sharing behavior, and spatial data locality. Our study reveals that these RMS workloads are memory intensive, have large working-set sizes greater than 16MB on average, exhibit a significant amount of data sharing, about47% on average, and show strong strided streaming access behavior with 77% of accesses in regular pattern. Based on the observations, we then investigate the potential cache architecture choices for future multi-core design. Our experiments show that for these workloads (a) large DRAM caches can be useful to address their large working sets; E.g., a 128MB DRAM cache can reduce the average L1 miss penalty by 18%; (b) shared last level cache provides better cache performance than private cache; E.g., a 8MB shared cache provides 25% performance improvement over a private one with the same total size; and (c) stride based hardware prefetcher provides significant performance benefit by 25%. As a result, we suggest a memory hierarchy with a 128MB DRAM cache, a 8MB on-die SRAM shared cache and an 8-entry stride prefetcher to accommodate RMS workloads.
Starting Page	153
Ending Page	160
File Size	394131
Page Count	8
File Format	PDF
ISBN	9780769536804
DOI	10.1109/ISPDC.2009.14
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-06-30
Publisher Place	Portugal
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multicore processing Random access memory Prefetching Scalability Distributed computing Computer science Microprocessors Character recognition Application software Hardware RMS workload workload characterization memory performance
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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