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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Petrowski, M. Clark, R. |
| Copyright Year | 2006 |
| Description | Author affiliation: Silicon Lab. Inc., Austin, TX, USA (Petrowski, M.; Clark, R.) |
| Abstract | Networking equipment must support a diverse and growing set of data rates including 10 G Ethernet, 10 G fibre channel, SONET OC-192 and the associated forward error correction (EEC) rates. Traditional timing sub-system architectures use a single crystal or SAW resonator for each frequency resulting in a plethora of individual oscillators on each port card. By using a DSP-based clock synthesis IC, multiple output frequencies can be generated from a single, low-frequency crystal resonator. Integrating the clock synthesis IC with the low-frequency quartz crystal into a hermetic ceramic package enables the development of multiple frequency crystal oscillator (XO) and voltage-controlled crystal oscillator (VCXO) devices. Key specifications, such as frequency stability, long-term aging, drift and mechanical integrity, are significantly improved over high-frequency fundamental (HFF) crystals or SAW-based oscillators. |
| File Size | 4661851 |
| File Format | |
| ISBN | 1557528039 |
| DOI | 10.1109/OFC.2006.215922 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-03-05 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | OSA |
| Subject Keyword | Timing Voltage-controlled oscillators Clocks Integrated circuit synthesis Frequency synthesizers Ethernet networks Optical fiber devices SONET Forward error correction Surface acoustic waves |
| Content Type | Text |
| Resource Type | Article |
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