NDLI: Large scale analog neural computer with programmable architecture and programmable time constants for temporal pattern analysis

Content Provider	IEEE Xplore Digital Library
Author	Van der Spiegel, J. Donham, C. Etienne-Cummings, R. Fernando, S. Mueller, P. Blackman, D.
Copyright Year	1994
Description	Author affiliation: Dept. of Electr. Eng., Pennsylvania Univ., Philadelphia, PA, USA (Van der Spiegel, J.; Donham, C.; Etienne-Cummings, R.; Fernando, S.)
Abstract	A large scale analog neural network has been built and tested for a number of applications. The network contains 1024 neurons with 94 synaptic inputs per neuron. The network is able to receive upto 3072 analog inputs. Among its unique features are the programmability of the architecture and the neural components allowing it to be used as a research and development tool for a large variety of applications. Also the network incorporates programmable time constants which makes it well suited for doing real-time or compressed time computations of temporal patterns. The operation of the neural network is fully analog and parallel, and runs independently of the digital host. The neural elements are custom designed and fabricated in a 1.5 /spl mu/m CMOS technology. They are grouped into three kind of chips: neuron chip, synapse chip, and the time constant and switch matrix chip. These chips or modules are placed on 16 printed circuit boards each containing 48 chips. Up to 3,072 buffered analog inputs and outputs are available.
Starting Page	1830
Ending Page	1835
File Size	692744
Page Count	6
File Format	PDF
ISBN	078031901X
DOI	10.1109/ICNN.1994.374436
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-06-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Large-scale systems Analog computers Computer architecture Neurons Neural networks CMOS technology Switches Testing Application software Research and development
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in