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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Rast, A. Galluppi, F. Davies, S. Plana, L.A. Sharp, T. Furber, S. |
| Copyright Year | 2011 |
| Description | Author affiliation: School of Computer Science, University of Manchester, UK (Rast, A.; Galluppi, F.; Davies, S.; Plana, L.A.; Sharp, T.; Furber, S.) |
| Abstract | Neural networks present a fundamentally different model of computation from conventional sequential hardware, making it inefficient for very-large-scale models. Current neuromorphic devices do not yet offer a fully satisfactory solution even though they have improved simulation performance, in part because of fixed hardware, in part because of poor software support. SpiNNaker introduces a different approach, the “neuromimetic” architecture, that maintains the neural optimisation of dedicated chips while offering FPGA-like universal configurability. Central to this parallel multiprocessor is an asynchronous event-driven model that uses interrupt-generating dedicated hardware on the chip to support real-time neural simulation. In turn this requires an event-driven software model: a rethink as fundamental as that of the hardware. We examine this event-driven software model for an important hardware subsystem, the previously-introduced virtual synaptic channel. Using a scheduler-based system service architecture, the software can “hide” low-level processes and events from models so that the only event the model sees is “spike received”. Results from simulation on-chip demonstrate the robustness of the system even in the presence of extremely bursty, unpredictable traffic, but also expose important model-evel tradeoffs that are a consequence of the physical nature of the SpiNNaker chip. This event-driven subsystem is the first component of a library-based development system that allows the user to describe a model in a high-level neural description environment and be able to rely on a lower layer of system services to execute the model efficiently on SpiNNaker. Such a system realises a general-purpose platform that can generate an arbitrary neural network and run it with hardware speed and scale. |
| Starting Page | 1967 |
| Ending Page | 1974 |
| File Size | 1467852 |
| Page Count | 8 |
| File Format | |
| ISBN | 9781424496358 |
| ISSN | 21614407 |
| e-ISBN | 9781424496372 |
| DOI | 10.1109/IJCNN.2011.6033466 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-07-31 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Computational modeling Algorithms Computer aided manufacturing Computer architecture Switches SDRAM Routing |
| Content Type | Text |
| Resource Type | Article |
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