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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Piuri, V. Sami, M.G. Sciuto, D. Stefanelli, R. |
| Copyright Year | 1992 |
| Description | Author affiliation: Dipartimento di Elettronica, Politecnico di Milano, Italy (Piuri, V.; Sami, M.G.; Sciuto, D.; Stefanelli, R.) |
| Abstract | When dedicated VLSI devices implementing application-specific neural networks are considered, the problem of testability evaluation and test pattern generation has to be solved. The authors analyze the abstract behavioral model of a class of neural networks (namely, feed-forward, multi-layered ones) with the aim of defining a general frame for testability evaluation and test pattern definition. Given such general results, for any given implementation it is sufficient to identify mapping between the behavioral error model and the physical fault model in order to evaluate the actual fault coverage that can be achieved and to identify a strategy for test pattern generation. When a particular silicon implementation is envisioned it is sufficient to map the actual physical faults onto the abstract error model in order to mathematically derive the testability conditions for the specific circuit. |
| Starting Page | 654 |
| Ending Page | 659 |
| File Size | 390412 |
| Page Count | 6 |
| File Format | |
| ISBN | 0780305590 |
| DOI | 10.1109/IJCNN.1992.226913 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1992-06-07 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Neural networks Circuit faults Test pattern generators Fault diagnosis Circuit testing Very large scale integration Pattern analysis Multi-layer neural network Feedforward neural networks Feedforward systems |
| Content Type | Text |
| Resource Type | Article |
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