NDLI: SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor

Content Provider	IEEE Xplore Digital Library
Author	Khan, M.M. Lester, D.R. Plana, L.A. Rast, A. Jin, X. Painkras, E. Furber, S.B.
Copyright Year	2008
Description	Author affiliation: Sch. of Comput. Sci., Univ. of Manchester, Manchester (Khan, M.M.; Lester, D.R.; Plana, L.A.; Rast, A.; Jin, X.; Painkras, E.; Furber, S.B.)
Abstract	SpiNNaker is a novel chip - based on the ARM processor - which is designed to support large scale spiking neural networks simulations. In this paper we describe some of the features that permit SpiNNaker chips to be connected together to form scalable massively-parallel systems. Our eventual goal is to be able to simulate neural networks consisting of $10^{9}$ neurons running in dasiareal timepsila, by which we mean that a similarly sized collection of biological neurons would run at the same speed. In this paper we describe the methods by which neural networks are mapped onto the system, and how features designed into the chip are to be exploited in practice. We will also describe the modelling and verification activities by which we hope to ensure that, when the chip is delivered, it will work as anticipated.
Starting Page	2849
Ending Page	2856
File Size	410433
Page Count	8
File Format	PDF
ISBN	9781424418206
ISSN	10987576
DOI	10.1109/IJCNN.2008.4634199
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-06-01
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Neurons Routing Computational modeling Magnetic cores Biological system modeling Delay Hardware
Content Type	Text
Resource Type	Article

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