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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Wong, C.Y. Lursinsap, C. |
| Copyright Year | 1989 |
| Description | Author affiliation: Center for Adv. Comput. Studies, Univ. of Southwestern Louisiana, Lafayette, LA, USA (Wong, C.Y.; Lursinsap, C.) |
| Abstract | Summary form only given. The authors propose a hardware-implementable, virtually connected, reconfigurable network architecture that has a high degree of fault tolerance. This architecture provides the neurons the ability of self-organization, and a neuron can establish a new synaptic connection that can be either excitatory or inhibitory, replacing a weakened old synapse. Cells are grouped into small partitions called cell cluster, and the communications among cells are limited within their influence regions. A message broadcasting algorithm which effectively limits the reach of the cells within their influence regions is described, and some illustrations of the fault tolerance characteristic of the architecture are given. By combining the cell clusters with the communication algorithm, a network with virtually no limit in size can be constructed. |
| File Size | 57578 |
| File Format | |
| DOI | 10.1109/IJCNN.1989.118402 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1989-01-01 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Computer fault tolerance Neural networks Parallel architectures Virtual computers |
| Content Type | Text |
| Resource Type | Article |
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