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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Jae-Hyeong Suh Yo-Han Lee Bum-Seok Suh Dong-Seok Hyun |
| Copyright Year | 1995 |
| Description | Author affiliation: Dept. of Electr. Eng., Hanyang Univ., Seoul, South Korea (Jae-Hyeong Suh; Yo-Han Lee; Bum-Seok Suh; Dong-Seok Hyun) |
| Abstract | A new low loss snubber circuit including overvoltage clamping circuit for a three-level GTO inverter is presented. The proposed snubber circuit is effective in the restriction of the dv/dt and the overvoltage values across each GTO at turn-off and the snubber loss is less than the half that of the conventional RCD snubber circuit. In addition, there is no blocking voltage balancing problem between the inner and the outer GTOs that occurs in the case when a conventional RCD snubber circuit is used in a three-level inverter topology. Experimental results demonstrate that the proposed snubber circuit is very effective for a large capacity three-level GTO inverter. |
| Starting Page | 290 |
| Ending Page | 295 |
| File Size | 598636 |
| Page Count | 6 |
| File Format | |
| ISBN | 0780330269 |
| DOI | 10.1109/IECON.1995.483410 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1995-11-06 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Snubbers Voltage control Circuit topology Pulse width modulation inverters Stress Inductors Transformers Switching circuits Switches Switching loss |
| Content Type | Text |
| Resource Type | Article |
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