NDLI: A high throughput low cost context-based adaptive arithmetic codec for multiple standards

Content Provider	IEEE Xplore Digital Library
Author	Keng-Khai Ong Wei-Hsin Chang Yi-Chen Tseng Yew-San Lee Chen-Yi Lee
Copyright Year	2002
Description	Author affiliation: Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan (Keng-Khai Ong; Wei-Hsin Chang; Yi-Chen Tseng; Yew-San Lee; Chen-Yi Lee)
Abstract	For next generation image compression standard, context-based arithmetic coding is adopted for improving the compression rate. An efficient and high throughput codec design is strongly required for handling high-resolution images. We propose an efficient codec architecture for context-based adaptive arithmetic coding, which exhibits low cost, low latency, and high throughput rate. In addition, it can be programmed for supporting multiple standards such as JPEG, JPEG2000, JBIG, and JBIG2 standards. It exploits three-pipeline stages architecture. Based on parallel leading zeros detection and bit-stuffing handling, symbols can be encoded and decoded within one cycle. Therefore, the throughput rate can be increased as high as the codec operating clock rate. For 0.35 /spl mu/ 1P4M CMOS technology, both the encoding and decoding rate can run up to 185 M symbol/sec. The AC codec only costs 12 K gate count and 860 /spl mu/m/spl times/860 /spl mu/m layout area. These performances can meet high-resolution real time application requirements.
Sponsorship	IEEE Signal Process. Soc
File Size	302986
File Format	PDF
ISBN	0780376226
ISSN	15224880
DOI	10.1109/ICIP.2002.1038164
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-09-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Throughput Costs Arithmetic Codecs Code standards Image coding Transform coding Decoding CMOS technology Delay
Content Type	Text
Resource Type	Article

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