NDLI: Design considerations of smart displays

Content Provider	IEEE Xplore Digital Library
Author	Miller, M.R.
Copyright Year	1998
Description	Author affiliation: Display Technol. Consulting, USA (Miller, M.R.)
Abstract	Flat panel display (FPD) technology is changing the rules governing the circuitry leading up to the display. This presents some problems, but also some opportunities to deliver images to the display in fundamentally different and possibly more efficient way than what is being done in a CRT dominated display world. The fact that matrix addressed FPDs require a sampled, usually digital signal dictates a different input approach. At the same time, the advantageous cost, performance and availability developments in memory and processing power drastically expand the choices of image data manipulation on the display. The capabilities of frame store memory and image compression-decompression affect the choices as to where we partition these functions as being on the display or in the system. The FPD provides a significant open area behind the display, which is very attractive as a place to integrate display functions. Several new display designs and materials seem to be ideal for this integration and for solving the problem of how to get the data from the processors on the back to the display on the front. The development of a smart display architecture will further impact designs such as a tiled display for very large, very high resolution images. In this case, each tile can be smart enough to render or decompress its part of the total image.
Starting Page	510
Ending Page	512
File Size	346798
Page Count	3
File Format	PDF
ISBN	0818688211
DOI	10.1109/ICIP.1998.723488
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-10-07
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer displays Flat panel displays Cathode ray tubes TV Image resolution Standards development HDTV Circuits Costs Availability
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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