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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Yviquel, H. Casseau, E. Raulet, M. Jaaskelainen, P. Takala, J. |
| Copyright Year | 2013 |
| Description | Author affiliation: Tampere Univ. of Technol., Tampere, Finland (Jaaskelainen, P.; Takala, J.) || IRISA, Univ. of Rennes 1, Rennes, France (Yviquel, H.; Casseau, E.) || IETR, INSA of Rennes, Rennes, France (Raulet, M.) |
| Abstract | The emergence of massively parallel architectures, along with the necessity of new parallel programming models, has revived the interest on dataflow programming due to its ability to express concurrency. Although dynamic dataflow programming can be considered as a flexible approach for the development of scalable applications, there are still some open problems in concern of their execution. In this paper, we propose a low-cost mapping methodology to map dynamic dataflow programs over any multi-core platform. Our approach finds interesting mapping solutions in few milliseconds that makes it doable at regular time by translating it in an equivalent graph partitioning problem. Consequently, a good load balancing over the targeted platform can be maintained even with such unpredictable applications. We conduct experiments across three MPEG video decoders, including one based on the new High Efficiency Video Coding standard. Those dataflow-based video decoders are executed on two different platform: A desktop multi-core processor, and an embedded platform composed of interconnected and tiny Very Long Instruction Word - style processors. Our entire design flow is based on open-source tools. We present the influence of the number of processors on the performance and show that our method obtains a maximum decoding rate for 16 processors. |
| Starting Page | 732 |
| Ending Page | 737 |
| File Size | 326217 |
| Page Count | 6 |
| File Format | |
| ISBN | 9789531841948 |
| DOI | 10.1109/ISPA.2013.6703834 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2013-09-04 |
| Publisher Place | Italy |
| Access Restriction | Subscribed |
| Rights Holder | University of Trieste and University of Zagreb |
| Subject Keyword | Program processors Decoding Streaming media Transform coding Multicore processing Video coding Dynamic scheduling |
| Content Type | Text |
| Resource Type | Article |
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