NDLI: Impact of pixel per processor ratio on embedded SIMD architectures

Content Provider	IEEE Xplore Digital Library
Author	Gentile, A. Wills, D.S.
Copyright Year	2001
Description	Author affiliation: Dipartimento di Ingegneria Autom. e Inf. Mater., Palermo Univ., Italy (Gentile, A.)
Abstract	A key design parameter for embedded SIMD architectures is the amount of image data directly mapped to each processing element defined as the pixel-per-processing-element (PPE) ratio. This paper presents a study to determine the effect of different PPE mapping on the performance and efficiency figures of an embedded SIMD architecture. The correlation between problem size, PPE ratio, and processing element architecture are illustrated for a target implementation in 100 nm technology. A case study is illustrated to derive quantitative measures of performance, energy, and area efficiency. For fixed image size, power consumption, and silicon area, a constrained optimization is performed that indicates that a PPE value of 4 yields to the most efficient system configuration. Results indicate that this system is capable of delivering performance in excess of 1 Tops/s at 2.4 W, operating at 200 MHz, with 16384 PE integrated in about 850 mm/sup 2/.
Sponsorship	Int. Assoc. Pattern Recognition (IAPR)
Starting Page	204
Ending Page	208
File Size	505306
Page Count	5
File Format	PDF
ISBN	076951183X
DOI	10.1109/ICIAP.2001.957009
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-09-26
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Streaming media Pixel Area measurement Energy measurement Energy consumption Silicon Constraint optimization Image processing Parallel processing Space exploration
Content Type	Text
Resource Type	Article

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