NDLI: MP3: Minimizing performance penalty for power-gating of Clos network-on-chip

Content Provider	IEEE Xplore Digital Library
Author	Lizhong Chen Lihang Zhao Ruisheng Wang Pinkston, T.M.
Copyright Year	2014
Description	Author affiliation: Ming Hsieh Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA (Lizhong Chen; Ruisheng Wang; Pinkston, T.M.) \|\| Inf. Sci. Inst., Univ. of Southern California, Los Angeles, CA, USA (Lihang Zhao)
Abstract	Power-gating is a promising technique to mitigate the increasing static power of on-chip routers. Clos networks are potentially good targets for power-gating because of their path diversity and decoupling between processing elements and most of the routers. While power-gated Clos networks can perform better than power-gated direct networks such as meshes, a significant performance penalty exists when conventional power-gating techniques are used. In this paper, we propose an effective power-gating scheme, called MP3 (Minimal Performance Penalty Power-gating), which is able to achieve minimal (i.e., near-zero) performance penalty and save more static energy than conventional power-gating applied to Clos networks. MP3 is able to completely remove the wakeup latency from the critical path, reduce long-term and transient contention, and actively steer network traffic to create increased power-gating opportunities. Full system evaluation using PARSEC benchmarks shows that the proposed approach can significantly reduce the performance penalty to less than 1% (as opposed to 38% with conventional power-gating) while saving more than 47% of router static energy, with only 2.5% additional area overhead.
Sponsorship	IEEE Comput. Soc.
Starting Page	296
Ending Page	307
File Size	817901
Page Count	12
File Format	PDF
ISBN	9781479930975
DOI	10.1109/HPCA.2014.6835940
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-02-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System-on-chip Ports (Computers) Logic gates Digital audio players Network topology Topology Power demand
Content Type	Text
Resource Type	Article

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