NDLI: Evaluation of a multithreaded architecture for cellular computing

Content Provider	IEEE Xplore Digital Library
Author	Cascaval, C. Castanos, J.G. Ceze, L. Denneau, M. Gupta, M. Lieber, D. Moreira, J.E. Strauss, K. Warren Jr., H.S.
Copyright Year	2002
Description	Author affiliation: IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA (Cascaval, C.; Castanos, J.G.; Ceze, L.; Denneau, M.; Gupta, M.; Lieber, D.; Moreira, J.E.; Strauss, K.; Warren, H.S., Jr.)
Abstract	Cyclops is a new architecture for high-performance parallel computers that is being developed at the IBM T. J. Watson Research Center. The basic cell of this architecture is a single-chip SMP (symmetric multiprocessor) system with multiple threads of execution, embedded memory and integrated communications hardware. Massive intra-chip parallelism is used to tolerate memory and functional unit latencies. Large systems with thousands of chips can be built by replicating this basic cell in a regular pattern. In this paper, we describe the Cyclops architecture and evaluate two of its new hardware features: a memory hierarchy with a flexible cache organization and fast barrier hardware. Our experiments with the STREAM benchmark show that a particular design can achieve a sustainable memory bandwidth of 40 GB/s, equal to the peak hardware bandwidth and similar to the performance of a 128-processor SGI Origin 3800. For small vectors, we have observed in-cache bandwidth above 80 GB/s. We also show that the fast barrier hardware can improve the performance of the Splash-2 FFT kernel by up to 10%. Our results demonstrate that the Cyclops approach of integrating a large number of simple processing elements and multiple memory banks in the same chip is an effective alternative for designing high-performance systems.
Sponsorship	IEEE Comput. Soc. Tech. Committee on Comput. Archit
Starting Page	311
Ending Page	321
File Size	359014
Page Count	11
File Format	PDF
ISBN	0769515258
ISSN	15300897
DOI	10.1109/HPCA.2002.995720
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-02-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Yarn Hardware Delay Bandwidth Parallel processing Silicon Logic Concurrent computing High performance computing
Content Type	Text
Resource Type	Article

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