NDLI: eXtended block cache

Content Provider	IEEE Xplore Digital Library
Author	Jourdan, S. Rappoport, L. Almog, Y. Erez, M. Yoaz, A. Ronen, R.
Copyright Year	2000
Description	Author affiliation: Intel Corp., USA (Jourdan, S.)
Abstract	This paper describes a new instruction-supply mechanism, called the eXtended Block Cache (XBC). The goal of the XBC is to improve on the Trace Cache (TC) hit rate, while providing the same bandwidth. The improved hit rate is achieved by having the XBC a nearly redundant free structure. The basic unit recorded in the XBC is the extended block (XB), which is a multiple-entry single-exit instruction block. A XB is a sequence of instructions ending on a conditional or an indirect branch. Unconditional direct jumps do not end a XB. In order to enable multiple entry points per XB, the XB index is derived from the IP of its ending instruction. Instructions within the XB are recorded in reverse order, enabling easy extension of XBs. The multiple entry-points remove most of the redundancy. Since there is at most one conditional branch per XB, we can fetch up to n XBs per cycle by predicting n branches. The multiple fetch enables the XBC to march the TC bandwidth.
Starting Page	61
Ending Page	70
File Size	99128
Page Count	10
File Format	PDF
ISBN	0769505503
DOI	10.1109/HPCA.2000.824339
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-01-12
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding Bandwidth Steady-state Iron Identity-based encryption Radio access networks Delay Degradation Information retrieval Out of order
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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