NDLI: Post-silicon code coverage evaluation with reduced area overhead for functional verification of SoC

Content Provider	IEEE Xplore Digital Library
Author	Karimibiuki, M. Balston, K. Hu, A.J. Ivanov, A.
Copyright Year	2011
Description	Author affiliation: Dept. of Computer Science, University of British Columbia (Hu, A.J.) \|\| Dept. of Electrical and Computer Engineering, University of British Columbia (Karimibiuki, M.; Balston, K.; Ivanov, A.)
Abstract	Effective techniques for post-silicon validation are required to better evaluate functional correctness of increasingly complex SoCs. Coverage is the standard measure of validation effectiveness and is extensively used pre-silicon. However, there is little data evaluating the coverage of post-silicon validation efforts on industrial-scale designs. In this paper, we address this knowledge gap. We have developed an industrial-size SoC, based entirely on open-source IP: roughly a “netbook-on-a-chip”, synthesizable to FPGA, and capable of running Linux, X11, and application software. This platform allows us to instrument the hardware to measure true post-silicon coverage achieved by typical post-silicon validation tests, such as booting the OS — tests that are impossibly expensive to run in pre-silicon simulation. Thus, we can compare coverage achieved pre — and post-silicon, and also measure the area overhead required to monitor post-silicon coverage. In addition, we apply state-of-the-art software analysis techniques to reduce the instrumentation overhead for coverage monitoring. Our results show: (1) The typical test of booting the OS often achieves high coverage, well correlated to what is achieved by pre-silicon directed tests, but in some blocks the coverage can be markedly different, highlighting the importance of post-silicon validation in general and post-silicon coverage measurement in particular. (2) The area overhead of the coverage monitoring instrumentation is high, ranging from 1% to 22%. (3) State-of-the-art software analysis techniques reduce the overhead (e.g., nearly a 30% reduction for one block we instrumented), but the remaining overhead is still unacceptably high for practical deployment. Taken together, our results provide a solid baseline for further research on post-silicon coverage and test generation.
Starting Page	92
Ending Page	97
File Size	671303
Page Count	6
File Format	PDF
ISBN	9781457717444
ISSN	15526674
e-ISBN	9781457717437
DOI	10.1109/HLDVT.2011.6113982
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-11-09
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System-on-a-chip Monitoring Instruments IP networks Silicon Booting
Content Type	Text
Resource Type	Article

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2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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