NDLI: IC design and verification approach at Ember

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2012 IEEE International High Level Design Validation and Test Workshop (HLDVT)

2011 IEEE International High Level Design Validation and Test Workshop

2010 IEEE International High Level Design Validation and Test Workshop (HLDVT)

2009 IEEE International High Level Design Validation and Test Workshop

2008 IEEE International High Level Design Validation and Test Workshop

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Table of contents

IC design and verification approach at Ember

Session 1: SOC verification methodologies

Positioning test-benches and test-programs in interaction-oriented system-on-chip verification

A method for hunting bugs that occur due to system conflicts

Applications of decorator and observer design patterns in functional verification

Session 2: Test

Test slice difference technique for low power encoding

Session 3: Panel - software practices for verification/testbench management

Panel: Software practices for verification/testbench management

Session 4: Formal verification

On dynamic switching of navigation for semi-formal design validation

Multi-level Bounded Model Checking to detect bugs beyond the bound

Proving and disproving assertion rewrite rules with automated theorem provers

Janus: A novel use of Formal Verification for targeted behavioral equivalence

Session 5: Invited session: On-chip instrumentation for silicon validation and debug

In-system silicon validation using a reconfigurable platform

On Chip Instrument application to SoC analysis

Session 6: Functional testing and verification

Test and validation of a non-deterministic system — True Random Number Generator

Functional testing approaches for “BIFST-able” tlm_fifo

IBM system z functional and performance verification using X-Gen

Timing verification of distributed network systems at higher levels of abstraction

Session 7: Simulation

Temporal parallel gate-level timing simulation

The role of parallel simulation in functional verification

A HW/SW co-simulation framework for the verification of multi-CPU systems

Session 8: Panel - SoC power management implications on validation and testing

Panel: SoC power management implications on validation and testing

Session 9: Special session: What’s so intelligent about testbenches?

Special session - What’s so intelligent about testbenches?

Session 10: Coverage and metrics

Optimized coverage-directed random simulation

Evaluation of an efficient control-oriented coverage metric

Session 11: Defect and fault models and test

High-level vulnerability over space and time to insidious soft errors

Automating defects simulation and fault modeling for SRAMs

Injecting intermittent faults for the dependability validation of commercial microcontrollers

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2006 IEEE International High Level Design Validation and Test Workshop

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Eighth IEEE International High-Level Design Validation and Test Workshop

Seventh IEEE International High-Level Design Validation and Test Workshop, 2002.

Sixth IEEE International High-Level Design Validation and Test Workshop

Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786)

IC design and verification approach at Ember

Content Provider	IEEE Xplore Digital Library
Author	LeFort, R.
Copyright Year	2008
Abstract	Ember develops ICs, software and tools for Wireless Sensor Networks. Our first IC was a transceiver co-developed with Chipcon (now part of TI) which is still sold today. We had so much fun co-developing that chip we decided to acquire our own IC Development team. The team developed a full networking SoC which includes a world class 2.4 GHz radio, a low power 16 bit core with 128 k Flash memory and 5 k SRAM. There are additional peripherals which allow full operation with the addition of a few external discrete devices, an antenna, and a power supply (which can be 2 AA batteries for 5+ years). The Ember IC Design approach is centered on a first time right design philosophy - something that is very hard to achieve in a complex mixed signal SoC. This includes designing and building analog test chips to confirm RF design blocks, complete emulators running application software, and completing over 500 system level test cases prior to tapeout. This strategy has proven to be successful on our first SoC as well as with our next generation device currently in characterization. The process, the tools, the expertise, and the discipline required to successfully manage this process will be presented. Mr. LeFort will also share observations and anecdotes from his 25 years in the semiconductor industry, starting with VSSI (Very Small Scale Integration) 3 um Bipolar Voltage Regulators through state of the art high performance mixed signal devices.
File Size	71822
File Format	PDF
ISBN	9781424429226
ISSN	15526674
DOI	10.1109/HLDVT.2008.4695863
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-19
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Signal design Software testing System testing Software tools Wireless sensor networks Transceivers Flash memory Random access memory Power supplies Batteries
Content Type	Text
Resource Type	Article

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