NDLI: Layout-Accurate Design and Implementation of a High-Throughput Interconnection Network for Single-Chip Parallel Processing

Content Provider	IEEE Xplore Digital Library
Author	Balkan, A.O. Horak, M.N. Gang Qu Vishkin, U.
Copyright Year	2007
Description	Author affiliation: Univ. of Maryland Inst. for Adv. Comput. Studies (UMIACS), Baltimore (Balkan, A.O.; Horak, M.N.; Gang Qu; Vishkin, U.)
Abstract	A mesh of trees (MoT) on-chip interconnection network has been proposed recently to provide high throughput between memory units and processors for single-chip parallel processing (Balkan et al., 2006). In this paper, we report our findings in bringing this concept to silicon. Specifically, we conduct cycle-accurate Verilog simulations to verify the analytical results claimed in (Balkan et al., 2006). We synthesize and obtain the layout of the MoT interconnection networks of various sizes. To further improve throughput, we investigate different arbitration primitives to handle load and store, the two most common memory operations. We also study the use of pipeline registers in large networks when there are long wires. Simulation based on full network layout demonstrates that significant throughput improvement can be achieved over the original proposed MoT interconnection network. The importance of this work lies in its validation of performance features of the MoT interconnection network, as they were previously shown to be competitive with traditional network solutions. The MoT network is currently used in an eXplicit multi-threading (XMT) on-chip parallel processor, which is engineered to support parallel programming. In that context, a 32-terminal MoT network could support up to 512 on-chip XMT processors. Our 8-terminal network that could serve 8 processor clusters (or 128 total processors), was also accepted recently for fabrication.
Starting Page	21
Ending Page	28
File Size	259581
Page Count	8
File Format	PDF
ISBN	9780769529790
ISSN	15504794
DOI	10.1109/HOTI.2007.11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-08-22
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Multiprocessor interconnection networks Parallel processing Network-on-a-chip Throughput Silicon Hardware design languages Analytical models Network synthesis Pipelines Registers
Content Type	Text
Resource Type	Article

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