NDLI: A Case Study in I/O Disaggregation using PCI Express Advanced Switching Interconnect (ASI)

Content Provider	IEEE Xplore Digital Library
Author	Krishnan, V. Comins, T. Stalzer, R. Wong, D.
Copyright Year	2006
Description	Author affiliation: StarGen Inc., Marlborough, MA (Krishnan, V.; Comins, T.; Stalzer, R.; Wong, D.)
Abstract	Decoupling the processor and I/O subsystem provides immense benefits that include high availability, efficient allocation and cost-effective upgrade of system resources. Such a disaggregation model calls for a high-performance interconnect to isolate the processor and I/O subsystem domains, yet provide the veneer of a single system. PCI express (PCIe) is one such interconnect and is becoming the de-facto I/O fabric. However, PCIe, as specified currently, provides limited support for I/O disaggregation and does not yet natively support dynamic sharing of I/O resources amongst processor subsystems - this is the next major step in I/O disaggregation. PCI express advanced switching interconnect (ASI) is well-suited for enhancing the capabilities of PCIe in a non-disruptive manner. ASI is built upon PCIe and has the innate ability to co-exist with PCIe devices due to its commonality of the link/physical layer with PCIe as well as its native support for encapsulating PCIe packets. Towards a simple yet illustrative demonstration of ASI-based disaggregation of PCIe devices, we employed StarGen's ASI products for creating a basic ASI fabric and disaggregated a PCIe based GigE NIC from a host system. The initial set of results showed a marginal effect on the application's latency, but contrary to expectations, the throughput was significantly impacted. Further analysis revealed that this unexpected drop in throughput could be rectified easily and indeed, the final results confirm that the use of ASI for supporting I/O disaggregation does not result in sub-optimal utilization of the GigE NIC
Sponsorship	IEEE CPS
Starting Page	15
Ending Page	24
File Size	332180
Page Count	10
File Format	PDF
ISBN	0769526543
ISSN	15504794
DOI	10.1109/HOTI.2006.5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-08-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches Fabrics Availability Resource management Throughput Bridges Physical layer Delay Costs Tunneling
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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