NDLI: Reducing capacity and conflict misses using Set Saturation Levels

Content Provider	IEEE Xplore Digital Library
Author	Rolan, D. Fraguela, B.B. Doallo, R.
Copyright Year	2010
Description	Author affiliation: Grupo de Arquitectura de Computadores, Departamento de Electrónica e Sistemas, Universidade da Coruña (Rolan, D.; Fraguela, B.B.; Doallo, R.)
Abstract	The well-known memory wall problem has motivated wide research in the design of caches. Last-level caches, whose misses can stall the processors for hundreds of cycles, have received particular attention. Strategies to modify adaptably the cache insertion, promotion, eviction and even placement policies have been proposed, some techniques being better at reducing different kinds of misses. For example changes in the placement policy of a cache, which are a natural option to reduce conflict misses, can do little to fight capacity misses, which depend on the relation between the working set of the application and the cache size. Nevertheless, other techniques such as the recently proposed dynamic insertion policy (DIP), whose aim is to retain a fraction of the working set in the cache when it is larger than the cache size, attack primarily capacity misses. In this paper we present a coordinated strategy to reduce both capacity and conflict misses by changing the placement and insertion policies of the cache. Our strategy takes its decisions based on the concept of the Set Saturation Level (SSL), which tries to measure to which degree a set can hold its working set. Despite requiring only less than 1% storage overhead, our proposal, called Bimodal Set Balancing Cache, reduced the average miss rate of a baseline 2MB 8-way second level cache by 16%, which translated into an average IPC improvement of 4.8% in our experiments.
Starting Page	1
Ending Page	9
File Size	292020
Page Count	9
File Format	PDF
ISBN	9781424485185
e-ISBN	9781424485208
e-ISBN	9781424485192
DOI	10.1109/HIPC.2010.5713184
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-19
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electronics packaging Radiation detectors Proposals Measurement Program processors Hardware Benchmark testing set saturation level Cache performance adaptivity balancing insertion replacement thrashing
Content Type	Text
Resource Type	Article

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