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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chao, H.J. |
| Copyright Year | 1991 |
| Description | Author affiliation: Bellcore, Red Bank, NJ, USA (Chao, H.J.) |
| Abstract | A queue management algorithm is described that manages the queued cells in such a way that higher-priority cells will always be sent to the links before the lower-priority ones, low-priority cells will be discarded when the queue is full, and same-priority cells are served fairly. The concept of assigning a departure sequence number to every cell in the queue is introduced so that the effects of the long-burst traffic to other regular arrival cells is avoided. Four architecture designs for queue management are presented, and their implementation feasibility and hardware complexity are compared. A novel architecture to implement the queue management is proposed. The architecture applies the concepts of fully distributed and highly parallel processing in order to schedule the cells sending or discarding sequences. The key VLSI chip used to implement the proposed architecture is described. |
| Starting Page | 1611 |
| Ending Page | 1618 |
| File Size | 571266 |
| Page Count | 8 |
| File Format | |
| ISBN | 0879426977 |
| DOI | 10.1109/GLOCOM.1991.188638 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1991-12-02 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Intelligent networks Switches Asynchronous transfer mode Traffic control Delay Interference Chaos Telecommunication traffic B-ISDN Packet switching |
| Content Type | Text |
| Resource Type | Article |
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