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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Olcer, S. |
| Copyright Year | 2003 |
| Description | Author affiliation: IBM Zurich Res. Lab., Ruschlikon, Switzerland (Olcer, S.) |
| Abstract | We describe a decoder architecture intended for decoding array-code-based low-density parity-check (LDPC) codes using the sum-product algorithm (SPA). The advantages of the proposed architecture, as compared to the fully parallel implementation of the SPA, are: reduced memory size, avoidance of complex signal interconnect patterns, and ease of programmability to accommodate various code parameters. These advantages are derived from exploiting the well-defined structure of the parity-check matrix of array-code based LDPC codes. Sum-product decoding with modified message-passing schedules are proposed to simplify the decoder implementation further. |
| Starting Page | 2046 |
| Ending Page | 2050 |
| File Size | 557092 |
| Page Count | 5 |
| File Format | |
| ISBN | 0780379748 |
| DOI | 10.1109/GLOCOM.2003.1258596 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2003-12-01 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Parity check codes Iterative decoding AWGN Sum product algorithm Processor scheduling Laboratories Parallel architectures Concurrent computing Computer architecture Additive white noise |
| Content Type | Text |
| Resource Type | Article |
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