NDLI: Performance analysis of a dual round robin matching switch with exhaustive service

Content Provider	IEEE Xplore Digital Library
Author	Yihan Li Shivendra Panwar, H. Chao, J.
Copyright Year	2002
Description	Author affiliation: Electr. & Comput. Eng. Dept., Polytech. Univ. Brooklyn, NY, USA (Yihan Li)
Abstract	Virtual Output Queuing is widely used by fixed-length high-speed switches to overcome head-of-line blocking. This is done by means of matching algorithms. Maximum matching algorithms have good performance, but their implementation complexity is quite high. Maximal matching algorithms need speedup to guarantee good performance. Iterative algorithms (such as PIM and iSLIP) use multiple iterations to converge on a maximal match. The Dual Round-Robin Matching (DRRM) scheme has performance similar to iSLIP and lower implementation complexity. The objective of matching algorithms is to reduce the matching overhead for each time slot. The Exhaustive Service Dual Round-Robin Matching (EDRRM) algorithm amortizes the cost of a match over multiple time slots. While EDRRM suffers from a throughput below 100% for small switch sizes, it is conjectured to achieve an asymptotic 100% throughput under uniform traffic. Simulations show that it achieves high throughput under nonuniform traffic. Its delay performance is not sensitive to traffic burstiness, switch size and packet length. In an EDRRM switch cells belonging to the same packet are transferred to the output continuously, which leads to good packet delay performance and simplifies the implementation of packet reassembly. In this paper we analyze the performance of an EDRRM switch by using an exhaustive service random polling system model. This was used to predict the performance of switches too large to be simulated within a reasonable run time.
Starting Page	2292
Ending Page	2297
File Size	484086
Page Count	6
File Format	PDF
ISBN	0780376323
DOI	10.1109/GLOCOM.2002.1189040
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-11-17
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches Performance analysis Round robin Iterative algorithms Throughput Traffic control Delay Packet switching Costs Predictive models
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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