NDLI: High-speed table lookup engine for IPv6 longest prefix match

Content Provider	IEEE Xplore Digital Library
Author	Hayashi, T. Miyazaki, T.
Copyright Year	1999
Description	Author affiliation: NTT Network Innovation Labs., Kanagawa, Japan (Hayashi, T.)
Abstract	This paper presents a hardware table-lookup (TLU) engine that allows the real-time operation of complicated TLU for telecommunications such as the longest prefix match (LPM) in IPv6 (128 bit-length address) protocol. The engine consists of a PLD (programmable logic device) and eight CAM (content addressable memory) chips which are divided into several groups. When actual TLU is performed, the entries in each CAM group are searched simultaneously, and the best entry candidate in each group is selected by a priority encoder which is implemented in the PLD. This grouping method with the priority encoder is the key to the scalability of the engine. We show that a TLU engine based on the above architecture achieves significantly better performance than those based on conventional software algorithms, especially in the case of a large number of entries. Furthermore, we note that our engine can support an over 300-K entry 2.5 Mpps line-rate LPM.
Starting Page	1576
Ending Page	1581
File Size	641646
Page Count	6
File Format	PDF
ISBN	0780357965
DOI	10.1109/GLOCOM.1999.830045
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-12-05
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Table lookup Engines Computer aided manufacturing CADCAM Hardware Protocols Programmable logic devices Associative memory Scalability Computer architecture
Content Type	Text
Resource Type	Article

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