NDLI: A broadband packet switch architecture with input and output queueing

Content Provider	IEEE Xplore Digital Library
Author	Chih-Yuan Chang Paulraj, A.J. Kailath, T.
Copyright Year	1994
Description	Author affiliation: Dept. of Electr. Eng., Stanford Univ., CA, USA (Chih-Yuan Chang; Paulraj, A.J.; Kailath, T.)
Abstract	The ATM is one of the most promising solutions for B-ISDN. Switch architectures based on Batcher-banyan networks are considered the most suitable for constructing large-dimension broadband packet switches. Though the Batcher-banyan network is internally nonblocking, the ubiquitous problem of packet loss resulting from outlet conflict can only be reduced by external buffering. Buffering strategies are basically categorized into two classes: input buffering and output buffering. For input-buffered switches, a phenomenon called head-of-the-line (HOL) blocking limits the maximum throughput to only 58.6 percent (2-/spl radic/2). On the other hand, output buffering achieves much higher throughput, but the entire switch has to be operated at a sufficiently high speed in order to deliver all the packets simultaneously destined for the same outlet. This generally imposes severe implementation problems. We propose a switch architecture with combined input and output queueing. The switch fabric consists of a Batcher sorting network, a radix-r shuffle mapping network, and r parallel distributing modules. The input queues and the switch fabric run at the same speed as the input and output trunks. However, up to r packets may arrive at an output queue in a single time slot. We analyze the throughput-delay characteristics of the proposed switch. The maximum throughput in the case where r=2 is 88.6 percent. For r=4, the proposed switch offers a 99.6 percent maximum throughput. In addition, the proposed switch relieves the HOL blocking by allowing up to r packets to be delivered to the same outlet in one time slot. Consequently, the average delay is also reduced.
Starting Page	448
Ending Page	452
File Size	562169
Page Count	5
File Format	PDF
ISBN	078031820X
DOI	10.1109/GLOCOM.1994.513561
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1994-11-28
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches Packet switching Throughput Fabrics Sorting Delay Asynchronous transfer mode Intserv networks Spine Road transportation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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