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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sieber, A.J. Lavalle, C. Slogget, D.R. |
| Copyright Year | 1994 |
| Description | Author affiliation: Joint Res. Centre, Commission of the Eur. Communities, Ispra, Italy (Sieber, A.J.; Lavalle, C.) |
| Abstract | The SAR processor is the basic element of the EARSEC processing chain. It will ingest raw data acquired by the EARSEC SAR sensors and will generate fully processed, calibrated, geocoded and georeferenced data. In addition the processor can generate, on request by the operator, intermediate products at any level of processing to allow the validation of the performed operations, to repeat them with changed parameters if the case, or to apply analysis tools for investigation and research purposes. To satisfy the software and hardware requirements, the adopted architecture is highly modular and flexible, ensuring portability and easy integration of different and new types of algorithms for each processing step. This concepts also allows the SAR kernel to be adopted for processing data from future SAR sensors without new sensible investment in coding. The selected hardware platform, based on a multi-processors SUN SPARC 1000 workstation equipped with 1 GByte of RAM, resulted the best combination of high performance (the goal being the processing of one fully polarimetric dual-frequency in about one hour) and friendly graphical user interface. The development of the EARSEC SAR processor, carried out by EOS(UK) for the JRC, first involves in a prototype version of each module in a high-performance computation environment (MatLab) and then in the coding of the final operational version that will be able to process data routinely and automatically. The processor, well suited to process data from several airborne and satellite (e.g. ERS series) SAR sensors and from the European Microwave Signature Laboratory, is one of a number of processing systems operating within an integrated environment for data and information fusion. |
| Starting Page | 1194 |
| Ending Page | 1196 |
| File Size | 263638 |
| Page Count | 3 |
| File Format | |
| ISBN | 0780314972 |
| DOI | 10.1109/IGARSS.1994.399383 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1994-08-08 |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Hardware Performance analysis Computer architecture Software algorithms Kernel Investments Sun Workstations Graphical user interfaces Prototypes |
| Content Type | Text |
| Resource Type | Article |
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