NDLI: A high-performance CMOS charge-pump for phase-locked loops

Content Provider	IEEE Xplore Digital Library
Author	Jianzheng Zhou Zhigong Wang
Copyright Year	2008
Description	Author affiliation: Inst. of RF- & OE-ICs, Southeast Univ., Nanjing (Jianzheng Zhou; Zhigong Wang)
Abstract	In order to improve the performance of the existing CMOS charge pumps (CPs), a systematical analysis of the existing CMOS CPs is presented. The nonideal effects such as mismatches, switch errors in CMOS CPs are quantitatively or qualitatively analyzed. Based on the circuit architecture, both classification and comparison are made. An improved CMOS single-ended CP is designed in SMIC 0.18-mum CMOS technology with 1.8-V supply voltage. In the CP, the switches are located at the source of the current mirror, and these switches are implemented using transmission gates driven by a couple of complementary clock signals. In addition, a large bypass capacitor is added to the CP. These circuits are used to make the CP avoid the switch errors. On the other hand, the charging current I $_{UP}$ and the discharging current I $_{DN}$ are both derived from the same supply-independent reference current source, and a high-gain folded-cascode operational amplifier is used to make the CP evade the sourcing/sinking current mismatch caused by the channel-length modulation effect of the current mirrors. The proposed CP only occupies an active area of 100 mum x 150 mu m. Post-simulation results reveal that the proposed CP has a wide output range, from 0.25 V to 1.62 V, and near perfect current matching characteristic. The current matching precision is better than 0.0105%.
Starting Page	839
Ending Page	842
File Size	886752
Page Count	4
File Format	PDF
ISBN	9781424418794
DOI	10.1109/ICMMT.2008.4540531
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-04-21
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Charge pumps Phase locked loops Switches CMOS technology Mirrors Performance analysis Voltage Coupling circuits Clocks Switched capacitor circuits
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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