NDLI: Software implementation of the OSIRIS iris recognition algorithm in FPGA

Content Provider	IEEE Xplore Digital Library
Author	Hentati, R. Abid, M. Dorizzi, B.
Copyright Year	2011
Description	Author affiliation: Institut Télécom; TélécomSudParis, Evry, 91011 (Dorizzi, B.) \|\| Research Unit CES, National school of Engineers of Sfax - Tunisia (Hentati, R.; Abid, M.)
Abstract	In this paper, we present a software implementation of an iris recognition algorithm on a FPGA (Field Programmable Gate Array). We use the OSIRIS reference systems developed in the framework of the BioSecure project which is an implementation of the well-knoun Daugman approach [10]. This system is composed of two modules. The first one uses the Hough transform to segment and normalize the iris. The second module applies a Gabor filter on the normalized image and calculates the similarity score between two images using the Hamming distance. OSIRIS algorithm has performance (EER=7.04%) when it is running on the PC in ICE 2005 Database. This system is coded in C++ using the library OpenCV (Open Source Computer Vision). This library is difficult to implement it in FPGA. that's why, we first remove this library in our code than improve this algorithm. Finally, we implement it on a CYCLONE II DE2 Board FPGA using the NIOS II processor which is characterized by its flexibility and programmability.
Starting Page	1
Ending Page	5
File Size	204286
Page Count	5
File Format	PDF
ISBN	9781457722073
e-ISBN	9781457722097
DOI	10.1109/ICM.2011.6177415
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-12-19
Publisher Place	Tunisia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Iris recognition Field programmable gate arrays Libraries Software algorithms Feature extraction Databases Signal processing algorithms NIOS II biometric iris recognition field-programmable gate arrays FPGA
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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