NDLI: A Digital Clock Re-Timing Circuit for On-Chip Source-Synchronous Serial Links

Content Provider	IEEE Xplore Digital Library
Author	Elrabaa, M.E.S.
Copyright Year	2006
Description	Author affiliation: Comput. Eng. Dept., King Fahd Univ. of Pet. & Miner. (KFUPM), Dhahran (Elrabaa, M.E.S.)
Abstract	A new all-digital circuit scheme for clock and data re-timing functions for on-chip high-speed source synchronous data communications, such as in burst-mode data transmission over a network-on-chip is introduced. The new technique is non-PLL-based and is capable of retiming the output clock with the received data within one data transition. Being fully digital makes its area much smaller than conventional circuitry. It can also be described by any hardware description language, simulated, and synthesized into any digital process. This enables it to be ported from one technology to another and support system on a chip (SOC) designs. The design concept is demonstrated with $T-Spice^{reg}$ simulations using a 0.13 mum digital CMOS technology.
Starting Page	206
Ending Page	209
File Size	2969356
Page Count	4
File Format	PDF
ISBN	1424407648
DOI	10.1109/ICM.2006.373303
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-12-16
Publisher Place	Saudi Arabia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Jitter Frequency Network-on-a-chip Phase locked loops Petroleum Minerals Data communication Circuit simulation CMOS technology Digital Circuits Clock-Recovery Networks-On-Chip Systems-on-Chip ASICs
Content Type	Text
Resource Type	Article

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