NDLI: 4K-cells Resistive and Charge-Base-Capacitive Measurement Test Structure Array (R-CBCM-TSA) for CMOS Logic Process Development, Monitor and Model

Content Provider	IEEE Xplore Digital Library
Author	Doong, K.Y.Y. Keh-Jeng Chang Lin, S.-C. Tseng, H.C. Dagonis, A. Pan, S.
Copyright Year	2009
Description	Author affiliation: Taiwan Semiconductor Manufacturing Company, Science-Based Industrial Park, Taiwan, No. 8, li-Hsin Sixth Rd., Hsin-Chu, Taiwan, R.O.C., Tel. +886-3-5636688 ext. 6855, e-mail: kelvin_doong@tsmc.com (Doong, K.Y.Y.) \|\| Taiwan Semiconductor Manufacturing Company, Science-Based Industrial Park, Taiwan, No. 8, li-Hsin Sixth Rd., Hsin-Chu, Taiwan, R.O.C., Tel. +886-3-5636688 ext. 6855 (Lin, S.-C.; Tseng, H.C.; Dagonis, A.; Pan, S.) \|\| Department of Computer Science, National Tsing Hua University, Hsin-Chu, Taiwan, No. 8, li-Hsin Sixth Rd., Hsin-Chu, Taiwan, R.O.C., Tel. +886-3-5636688 ext. 6855 (Keh-Jeng Chang)
Abstract	To maximize the design efficiency of the test chip area and maintain the high accuracy measurement requirement of resistors and capacitors, a 4K-cells resistive and charge-base capacitive test structure array is designed for CMOS logic process development, monitor and model. The test chip utilizes 4-terminal (one of 4 is strongly grounded) Kelvin force/sense measurement for resistive-type and charge-base capacitance measurement (CBCM) for capacitive-type test structures. With the aid of memory-addressing design scheme, any one of the device-under-test in an array can be randomly or sequentially selected for testing with all of them sharing a common probe pad group. To accelerate the testing speed, the address control signals of 8 test structure array are connected in parallel for synchronized parallel testing. A 32×16×8 test structure array has been implemented by utilizing a state-of-the-art logic process to demonstrate design feasibility. The results confirm the excellence of this architecture in measurement with 0.1fF for capacitive and 0.1 ohm for resistive systematic errors, and 7 times testing speed improvement.
Starting Page	216
Ending Page	220
File Size	5275246
Page Count	5
File Format	PDF
ISBN	9781424442591
DOI	10.1109/ICMTS.2009.4814645
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-03-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic testing Logic arrays Current measurement CMOS process CMOS logic circuits Monitoring Semiconductor device modeling Semiconductor device measurement Logic design Force measurement
Content Type	Text
Resource Type	Article

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