NDLI: Application of Matching Structures to Identify the Source of Systematic Dimensional Offsets in GHOST Proximity Corrected Photomasks

Content Provider	IEEE Xplore Digital Library
Author	Smith, S. Tsiamis, A. McCallum, M. Hourd, A.C. Stevenson, J.T.M. Walton, A.J.
Copyright Year	2009
Description	Author affiliation: Compugraphics International Ltd., Eastfield Industrial Estate, Glenrothes, Fife, KY7 4NT, UK (Hourd, A.C.) \|\| Nikon Precision Europe GmbH, Appleton Place, Appleton Parkway, Livingston, West Lothian, EH54 7EZ, UK (McCallum, M.) \|\| Institute for Integrated Micro and Nano Systems, School of Engineering, Scottish Microelectronics Centre, The University of Edinburgh, EH9 3JF, UK (Tsiamis, A.; Stevenson, J.T.M.; Walton, A.J.) \|\| Institute for Integrated Micro and Nano Systems, School of Engineering, Scottish Microelectronics Centre, The University of Edinburgh, EH9 3JF, UK. Email: Stewart.Smith@ed.ac.uk (Smith, S.)
Abstract	The effects of the GHOST proximity correction process on chrome-on-quartz photomasks can prove difficult to quantify and so they are not routinely characterised. This paper presents a methodology for addressing this issue using electrical test structures designed to measure dimensional mismatch. In the past these have been used successfully to characterise standard GHOSTed photomasks, which displayed systematic offsets that were not seen on an unGHOSTed mask using the same design. In order to investigate this further, a second mask was fabricated using a variation of the GHOST process which increased the resolution of the secondary exposure to be the same as the primary pattern. This enabled the source of the previously observed systematic offset to be determined as test structures on the new mask did not show the same overall dimensional bias. However, the range of mismatch in some of the structures was increased as a result of the new process.
Starting Page	50
Ending Page	55
File Size	677520
Page Count	6
File Format	PDF
ISBN	9781424442591
DOI	10.1109/ICMTS.2009.4814609
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-03-30
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Testing Resistors Bridge circuits Electric resistance Electrical resistance measurement Electric variables measurement Metrology Current measurement Systems engineering and theory Microelectronics
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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