NDLI: Test chip characterization of X architecture diagonal lines for SoC design

Content Provider	IEEE Xplore Digital Library
Author	Arora, N.D. Song, L. Shah, S. Joshi, K. Thumaty, K. Fujimura, A. Schoellkopf, J.P. Brut, H. Smayling, M. Nagata, T.
Copyright Year	2004
Description	Author affiliation: Cadence Design Syst. Inc., San Jose, CA, USA (Arora, N.D.; Song, L.; Shah, S.; Joshi, K.; Thumaty, K.; Fujimura, A.)
Abstract	This paper addresses the manufacturability, yield and reliability aspects of an X architecture (diagonal lines) silicon-on-chip (SoC) design that enables IC chips to become faster and smaller (area) compared to the same design in a Manhattan structure. Test chips that consist of comb/serpentine, maze, via chain, as well as resistance and capacitance structures are designed and fabricated using both a 130 nm and a 90 nm copper CMOS processes. The measurements of the line resistance (Kelvin structures), capacitance (inter-digited structure) and SEM data show that for 1:1 design rules (Manhattan vs. X architecture), the uniformity and fidelity of the diagonal lines are as good as Manhattan lines. The current generation of mask, lithography, and wafer processing techniques are applicable to X architecture designs.
Sponsorship	IEEE Electon Devices Soc
Starting Page	75
Ending Page	79
File Size	423871
Page Count	5
File Format	PDF
ISBN	0780382625
DOI	10.1109/ICMTS.2004.1309305
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-03-22
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Testing Wire Copper Delay System-on-a-chip Integrated circuit interconnections Capacitance Routing Dielectrics Artificial intelligence
Content Type	Text
Resource Type	Article

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