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A thermal van der Pauw test structure

Content Provider	IEEE Xplore Digital Library
Author	Paul, O. Plattner, L. Baltes, H.
Copyright Year	1999
Description	Author affiliation: Inst. for Microsyst. Technol., Freiburg Univ., Germany (Paul, O.)
Abstract	A micromachined thermal van der Pauw test structure is reported. Similar in principle to the conventional electrical van der Pauw Greek cross test structures, it enables the in-plane thermal sheet conductivities of thin films to be determined. The analogy between the two-dimensional heat flow in thin film samples and the electrical current pattern in thin film conductors is exploited. A thermal sheet resistance of 1.87/spl times/10/sup 5/ K/W was extracted from the complete sandwich of dielectric layers of a commercial CMOS ASIC process. This is equivalent to an average in-plane thermal conductivity of the CMOS dielectric layer sandwich of /spl kappa/=1.44 Wm/sup -1/ K/sup -1/.
Starting Page	56
Ending Page	61
File Size	778009
Page Count	6
File Format	PDF
ISBN	078035270X
DOI	10.1109/ICMTS.1999.766216
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-03-15
Publisher Place	Sweden
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Density estimation robust algorithm Testing Thermal conductivity Dielectric thin films Conducting materials Contacts Heating Resistors Current density Slabs
Content Type	Text
Resource Type	Article

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