NDLI: SystemVerilog assertion for microarchitecture education considering situated nature of learning: A senior project

Content Provider	IEEE Xplore Digital Library
Author	Takahashi, R. Takefuji, Y.
Copyright Year	2011
Description	Author affiliation: Faculty of Information Sciences, Hiroshima City University, Hiroshima, 731-3194, Japan (Takahashi, R.) \|\| Faculty of Environment and Information Studies, Keio University, Kanagawa, 252-8520, Japan (Takefuji, Y.)
Abstract	SystemVerilog assertion (SVA) is a way to express properties that are expected to be true in a design described in Verilog HDL IEEE1364 standard. We have already reported that legitimate peripheral participation (LPP) works very well for the fine grain microprocessor design education on FPGA where the heart of the system is chosen as the way-in which is the first step for the observation in LPP. We have demonstrated its effectiveness on superscalar design education, while the prior pipeline design education failed. The failure was caused by the top down design methodology guided in the education for the pipelining which appeared to be too difficult. Appropriate scheme to observe the heart of the pipelining is needed. We have found that SVA plays a key role where two senior students succeeded to design pipelined RISC having 3 stages and pipelined CISC having 4 stages in 2 months. White box test by using SVA enables the two senior students to observe the heart of the pipelining very effectively.
Starting Page	112
Ending Page	113
File Size	863379
Page Count	2
File Format	PDF
ISBN	9781457705489
e-ISBN	9781457705519
e-ISBN	9781457705502
DOI	10.1109/MSE.2011.5937107
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-06-05
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Education Reduced instruction set computing Pipeline processing Hardware design languages Heart Field programmable gate arrays Microarchitecture Microarchitecture education SystemVerilog Assertion Legitimate peripheral participation Ppipelining
Content Type	Text
Resource Type	Article

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